Firmware, mostly. The PSoC 6 Blackjack project is all C on FreeRTOS: seven state tasks, a gatekeeper task for each bus, queues and notifications between them, and hand-written drivers for the joystick, buttons, SPI, I2C, and UART underneath.

The eBike controller for ECE 551: 20 SystemVerilog modules from SPI master to PID to commutation, synthesized to 32 nm. The ECE 552 pipelined CPU in structural Verilog, down to dff primitives. On the capstone, teammates wrote the classifier RTL and my PS-side pipeline had to match its AXI-Lite register map and timing exactly.

Synthesizing the eBike controller to SAED 32 nm LVT at a 2.5 ns clock: constraints, wire-load model, hold fixing, and reading the area and timing reports. An area-driven compile_ultra experiment cut cell area 18% but left one hold path 80 ps short, which is why it didn't become the final netlist.

Closed-loop system testbenches through physics models for the eBike controller, unit benches for every block, gate-level simulation of the synthesized netlist, and cycle-level traces of four test programs on the pipelined CPU.

The Infineon board under the Blackjack project: ADC joystick, GPIO buttons, SPI EEPROM, a TCA9534 I2C IO expander, a parallel-bus LCD, and a UART console, each behind its own FreeRTOS gatekeeper task so only one piece of code ever touches a bus.

The core in the PSoC 6. Interrupt-context work on it (an IO-expander ISR posting to an event group through the FromISR API), task priorities set so input preempts the game state machine, and the timing questions that come with both.

Block design and IP integration on the AUP-ZU3 for the capstone: the DPU build that routed and closed timing but consumed the whole device, and the custom MLP peripheral that replaced it. Most of the work is reading the reports after a build, not the build itself.

The Zynq UltraScale+ XCZU3EG on the AUP-ZU3 board. Getting the processing system and the programmable logic to cooperate — clocking, the AXI interfaces, shared memory, and booting into PYNQ — was most of the capstone.

The register interface between the ARM cores and the capstone's FPGA classifier: 34 keypoint values written in, a class read back. My side was the processing system: writing to and reading from that peripheral from Python on PYNQ, and making the camera pipeline feed it at frame rate.

How the capstone's Python side talks to the fabric: loading the overlay, mapping the MLP peripheral's registers, and driving inference from the same script that runs the camera.

The Whack-a-Mole board: layout in Altium from a provided schematic, fabrication, hand assembly, and bring-up, which turned up a schematic error I fixed on the board with a cut trace and a jumper.

Full-custom layout for the ECE 555 MLP classifier: a ReLU multiplexer cell on the team's 11.88 µm bit-slice pitch, integrated into the datapath and verified DRC and LVS clean with parasitic extraction.

Thirteen tasks on the PSoC 6: one per Blackjack game state, one gatekeeper per peripheral, wired together with task notifications, an event group, queues that carry their own reply-queue handles, and a binary semaphore around the game struct. Built in ModusToolbox with GCC ARM.

My default for anything data or ML: the preprocessing pipeline at Veridis, the EEG pipeline from EDF files through MNE to spectrograms, model training in both PyTorch and TensorFlow, the OpenCV and NumPy camera pipeline on the capstone's ARM cores, and the FastAPI services I've written since.

Trained regression and classification models on 23-channel time-series sensor data at Veridis, and the 1D and 2D CNNs in the EEG seizure project, where the model was fine and the evaluation was the problem.

Used alongside PyTorch at Veridis to compare architectures against the same preprocessed sensor data.

Tracked 20+ training configurations at Veridis — parameters, metrics, and artifacts — so runs could be compared later rather than remembered.

At Radius Signal I tested the Gemini-backed candidate screening workflow, found bugs in it, and fixed them; the evaluation and testing for Radius Talent, the product I'm on now, are mine to build. The Goal Planner is where I've already built that side end to end: three Claude agents on the Anthropic SDK, structured outputs constrained to Zod schemas, typed fallbacks so the app never fails because the model did, and an eval harness with an LLM judge that decides which model each agent runs on.

In the Goal Planner, every model call is logged with tokens, cost, and latency, and an eval harness with deterministic checks and an LLM judge decides which model each agent runs on. Built first, on purpose: it found six bugs the unit tests couldn't see.

Google's pretrained MoveNet pose model, run through TFLite on the capstone's ARM cores to turn each camera frame into 17 keypoints before anything reaches the fabric.

Camera capture and the on-screen overlay for the capstone: skeleton, class, confidence, rep count, and frame rate drawn onto the DisplayPort output.

The runtime for the DPU integration attempt on the capstone. I built the camera → shared-memory → VART inference path on the processing-system side before the team moved pose estimation off the fabric.

The three classical baselines in the EEG project, and the metrics that showed accuracy was lying: sensitivity, AUC, and thresholds chosen on validation data against a false-alarm budget.

This site, end to end. The projects and skills you're reading are typed data in one folder, so adding either one is a data change rather than a template change.

The Goal Planner is a full Next.js 14 app with Postgres behind it. This site is the other kind — exported to static HTML, which is why it can sit in an S3 bucket behind a CDN with no server to keep running.

The second-round interview scheduling service at Radius Signal: a FastAPI service on the WhatsApp Business API that parses candidate replies, proposes slots, and writes confirmed interviews to the calendar. Also the messaging service that fronts several third-party messaging APIs.

The Goal Planner runs on Postgres through Prisma: goals, milestones, scheduled tasks, the per-call telemetry table, and the rate-limit windows, which are one atomic upsert per request. Database Management coursework covered the theory; that project is where it got real.

Containerized the FastAPI services at Radius Signal, so they run the same locally as they do on AWS. Before that, Docker Compose for the Flight Tracker so the frontend and backend came up with one command.

Containerized services at Radius Signal, and this site — S3, CloudFront, and Route 53, with an OIDC role for CI, all defined in Terraform.

The deploy pipeline for this site: lint, typecheck, build, sync to S3, then invalidate the CloudFront cache. It authenticates to AWS over OIDC, so there are no stored access keys. The Flight Tracker had the same idea on GitLab CI: build and test on every change, before code review.

The Goal Planner's runtime under Next.js, and the Radius Signal platform, where the placement-offer module with DocuSign and the per-company intro video pipeline live.

The Flight Tracker backend: a Spring Boot REST service in front of the FlightAware and OpenSky APIs, with rate-limit handling so the UI gets a clear message rather than a failed request. Built with a six-person Scrum team where I was the primary developer.