MLP Classifier in Full-Custom VLSI

A small neural network built as full-custom silicon for ECE 555 (VLSI) at UW–Madison, with a team of four. Two inputs, an accelerometer and a stretch sensor, feed two hidden neurons and one output neuron, and the network classifies sit versus run. Each neuron is a multiply-accumulate unit followed by a ReLU activation. Inputs are 2-bit unsigned; the weights are fixed 2-bit signed values hardcoded into the design.

There is no general multiplier. Because the weights are fixed, multiplication reduces to shifts and two's complement, and 4-bit adders sum the products and the bias. ReLU is a mux that selects either zero or the sum based on the sign bit.

The layout is full-custom cells in Cadence Virtuoso, arranged as a bit-slice datapath on a required 11.88 µm pitch. Power runs as M1 rails along each slice, M2 straps across them, and M3 VDD and VSS delivery per slice.

The team verified each block and then the full design DRC and LVS clean, ran parasitic extraction on both, and simulated post-layout.

My part: I laid out the ReLU multiplexer cell and helped wire the cells into the full perceptron. It makes a neat pair with the Flex-PGA capstone: both are hardware activity classifiers, one in custom silicon and one in an FPGA's fabric.