16-bit Pipelined RISC CPU with Caches

A 16-bit RISC processor designed and verified in structural Verilog with Thomas and Ashton for ECE 552 (Computer Architecture) at UW–Madison. It implements a 16-instruction custom ISA with N, V, and Z flags and eight branch conditions. All three of us worked across every part of the design rather than splitting it into silos.

The core is a classic IF/ID/EX/MEM/WB pipeline. The hazard unit detects load-use and branch-source stalls, MEM and WB results forward back to EX with a byte-merge so partial-register writes forward correctly, and branches resolve in ID with a flag bypass so a taken branch flushes a single instruction.

Behind it sits a memory hierarchy: separate 2 KB two-way set-associative instruction and data caches, each 64 sets of 16-byte blocks with LRU replacement, a write-through data cache, a fill FSM that streams 8-word blocks from a 4-cycle-latency main memory, and an arbiter that gives the data cache priority when both miss at once.

The datapath includes a 16-bit carry-lookahead adder, saturating ADD and SUB, a four-lane packed saturating add (PADDSB), a byte-reduction tree (RED), and a logarithmic shifter for SLL, SRA, and ROR, plus a bit-cell register file with byte-granular writes.

Everything is structural Verilog: every register is built from a dff primitive, and a Design Compiler script targets a 2.5 ns clock in a 32 nm library. Verification ran four assembled test programs, including a self-checking memory-copy loop, and all four pass with cycle-level simulation traces.