M1dpu-bringup
DPU Bring-Up on a ZU3
Integrated the DPUCZDX8G IP in Vivado on an AUP-ZU3 (ZynqMP) board targeting pynq-dpu inference.
The ZU3 doesn't really have room for it, so the work was mostly negotiation: scaled the DPU down to a B512 configuration to fit, and dropped the PL1 clock to 200 MHz to close timing.
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